Owen Deng
Electrcial and Computer Engineering
Cornell University, Ithaca NY
qd39 at cornell dot edu
Programming Skills
SW: Python, C/C++
HW: Verilog, SystemVerilog
Others: Linux, Bash, Git, Perforce, AWS, Azure, Docker, Vitis HLS
Other Engineering Skills
Electrical Measurements, Circuit Analysis, Semiconductor Processing, Materials Characterization, FPGA
Languages
English - bilingual proficiency
Mandarin - native
Cantonese - native
Update 2022/12/25: I am no longer maintaining this page... For the most up-to-date information, please refer to my github profile page or my LinkedIn.
Education
Cornell University
Aug. 2018 - Dec. 2022 (expected)
B.S. (2021) and M.Eng. (current) in Electrcial and Computer Engineering
CS Courses: Cloud Computing, Systems Programming, Computer Networks, Computer Vision, Machine Learning
EE Courses: Computer Architecture, Embedded Systems, Advanced MCU Design, Design of Fast Robots, DSP
Experience
Design Verification Intern at Apple (Neural Engine)
Aug. 2021 - Dec. 2021
- Performed both functional and performance verification on Apple Neural Engine RTL design
- Improved and maintained SystemVerilog testbench infrastructure
- Developed reference models in C++ and integrated via SystemVerilog DPI-C interface
- Reviewed design and architectural specs, created & executed tests/coverage plans, debugged failures
- Collaborated with the design and micro-architecture team to understand functional and performance goals
Software Engineer Intern at PureFDA
Jun. 2020 - Jun. 2021
- Designed, implemented, and deployed an autonomous, modular, and extensible medical devices big data platform (data warehouse, ETL pipelines, etc.) in Python
- Connected the data platform with 20+ live online data sources with point-in-time history tracking
- Designed and implemented a serverless cloud architecture (Azure)
- Set up build, test, deploy automation pipelines with Docker containers
- Coordinated with front-end engineers to specify and implement REST API for database query handling
- Wrote technical documentation and drafted patent applications
Undergraduate Research - McMahon Lab
May. 2020 - May. 2021
- A novel Boolean satisfiability (SAT) solver on FPGAs
- Implementation with Vitis HLS by Xilinx and AWS EC2 F1 for deployment
- Analyzed bottlenecks and identified optimization possibilities
- Achieved performance comparable to state of the art SAT solvers
Projects
Please visit my GitHub page and my LinkedIn project section for a comprehensive list of projects I've worked on.